Using Ansys Simulation for High-Speed SerDes Channel Verification

Task Description

Darknote Engineering was tasked with verifying a high-speed SerDes (Serializer–Deserializer) channel operating at 10.3125 Gbps for a custom electronic module. The project involved a short-reach backplane configuration with selective signal path switching and strict signal integrity requirements. With a unit interval under 100 ps and lossy PCB materials, the design demanded early, accurate electromagnetic validation to avoid costly redesigns.

Pic. 1 Modeling of PCB structures

Solution

ANSYS HFSS: Used to model complex PCB structures including differential vias, MLCC capacitors, fan-out routing, and switch geometries. Simulations provided detailed frequency-domain characterization of insertion and return loss across the 10+ GHz spectrum.

ANSYS SIwave & AEDT (Advanced Electronics Desktop): Enabled full-channel SI validation using IBIS-AMI models and Touchstone files. Eye diagrams and impulse responses were simulated with and without active equalization to assess channel compliance.

Pic. 2: Ansys EM simulation flow for SI

Benefits

• Eliminated 2 board redesign cycles, saving approximately €18,000 in prototyping and validation costs.

• Reduced development time by 6 weeks through early virtual compliance testing.

• Achieved a 23% improvement in insertion loss margin over the initial design, validated before first fabrication.

• Improved eye opening up to 31% by using custom settings determined by simulation for FFE and CTLE equalization, avoiding PCB cost increase due to stack-up changes