Mixed-signal Power Integrity and Reliability Analysis
Ansys Totem is a transistor-level power noise and reliability simulation platform for noise coupling analysis of analog, mixed-signal and custom digital designs. It helps designers meet increasingly stringent power and reliability requirements for IPs, analog and custom IC designs. Totem enables design analysis while taking package and substrate parasitics into account, with SPICE-level accuracy. It is qualified for design verification and sign-off for process technologies down to 7 nm.
The convergence of advance process technology, increasing levels of integration and higher operating frequencies pose considerable challenges to IP designers whose circuits are required to function in variety of conditions. One key aspect for reliable operation of these complex circuits is the quality of the voltage supply they receive. Existing methods do not provide sufficient capabilities to predict the impact of power and ground supply fluctuation on various key circuit parameters, like noise margin, clock jitter and delays.
Ansys Totem offers a comprehensive cosimulation framework for analog, mixed-signal and custom circuit designers. It analyzes static (IR, EM) and dynamic noise (DvD1) for the power and ground network at the IP or full-chip level along with the impact of current flow on signal lines (signal EM). Totem provides a comprehensive full-chip solution for modeling and simulating noise injection, propagation and coupling through the on-die power grid RLC, substrate RC, and package RLC networks.
Integrated Analog and Custom Circuit Simulation Platform
Our layout-based analog and custom circuit simulation platform is ideal for power noise and reliability analyses. Totem uses a single-pass flow that can be applied to early layout connectivity analysis, static voltage drop verification, dynamic power noise sign-off, power/signal net electromigration (EM) analyses and substrate noise coupling verification. The software displays results in a rich GUI environment; it also generates data reports, maps and waveforms for debugging.
Totem’s connectivity checks help you to quickly identify layout issues, such as missing vias, shorts and unconnected or weakly connected devices. Network topology analysis provides insight into routing issues that might cause voltage drop hot-spots or current congestions. You can perform connectivity analysis early in the design stage, soon after design layout is available ― you don’t need to wait for post-layout signal net extraction and SPICE characterization of device currents.
Static IR Analysis
Totem static IR analysis verifies the robustness of the power grid, performing DC analysis with transistors drawing a steady-state current. It provides considerable flexibility in assigning transistor-level current. For example, by specifying a total current target, Totem can distribute it using device sizes or other parameters, or by specifying the current target for a specific region or netlist hierarchy. You can modify or update the current drawn at any or all transistors through interactive current assignment and modification options. These techniques enable flexible IR/EM analysis from early stage to sign-off, while maintaining consistency required for sign-off analyses.
Dynamic Voltage Drop
Dynamic voltage drop analyses with Ansys Totem helps to expose design weaknesses caused by simultaneous switching of transistors, accounting for inductive and capacitive parasitics of the power delivery network, including package and PCB. Unlike static simulation, in which the current drawn can be modified based on various settings, Totem’s dynamic voltage drop analysis reflects the actual operation of the circuit, time-varying current drawn and interplay of the various parasitics causing the power droop or ground bounce.
There are extensive early-analysis capabilities that allow designers to explore various power-grid architectures. For example, the interactive power assignment enables early-design dynamic analysis based on user-defined power-noise scenarios.
Substrate Noise Coupling
Totem helps you to analyze the impact of substrate noise coupling from noisy digital circuitry to sensitive analog and RF blocks. Substrate analysis enhances full-chip power noise sign-off, guard ring structure design and verification, substrate noise impact on timing simulation, and frequency domain analysis. Totem’s substrate noise analysis has been well correlated with silicon measurements.
Totem provides a single platform for power and signal interconnect electromigration (EM) analyses, supporting EM rules for sub-20 process technologies. Current direction-aware extraction allows accurate current flow modeling in wide metal structures; it considers the shape and routing of specific via array, which helps in reducing false EM violations. EM results are easily checked and analyzed in the layout-based environment, resulting in quick design edit and fixing.
Signal EM analysis is performed for average, RMS and peak current densities for all signal wires and vias. It supports unified run with separate unidirectional and bidirectional current analysis. Totem validates signal EM on flattened transistor-level designs and block-level inter-cells for embedded digital blocks. Its layout-based GUI with cross-probing capabilities provides easy-to-use and robust debugging, including detailed violation reports with current values and their directions.
Accuracy and Capacity
Totem concurrently analyzes noise propagation through the entire power delivery network, from system/PCB to on-chip power grid and substrate network. Such accuracy means that analysis correlates very closely with silicon measurements ― Totem results have been validated by many customers, including those designing IPs and other custom circuits using advanced technology nodes.
The multi-CPU architecture and advanced solvers enable flat simulation of 100+ million transistor designs. Totem can perform hierarchical simulation using CMM technology. For ultra-large designs, Totem utilizes mesh pattern recognition (MPR) to deliver high capacity and run time benefits. MPR uses both circuit element pattern recognition and network reduction to increase analysis performance as well as memory requirements, especially for dense power/ground grids.
Layout-Based Debug and Root-Cause Analysis
The GUI offers full visibility into the cause of failures, since it overlays simulation results on top of the layout. This allows for quick interactive root-cause analysis and what-if fixing, which significantly reduces the debug cycle. Totem’s versatile, multi-functional GUI gives the look-and-feel of a layout editor while providing full visibility into simulation results through sophisticated multi-tab, multi-pane capabilities.
Totem Explorer is a self-debugging GUI for design and data integrity validation, design weakness checks and hot-spot root cause analysis. It is tightly integrated with the Totem GUI and provides an easy-to-use cross-probing capability.
IP Validation and Sign-off
Totem enables complete IP validation and sign-off flow. It verifies and analyzes an IP during its design phase; it also verifies that the IP is used appropriately at the SoC level. This consistent and robust verification methodology ensures that the IP will perform to specifications at the SoC level.
IP designers can use Totem to embed sign-off constraints, such as connectivity limits and voltage drop thresholds, and the embedded rules are verified for compliance during the SoC-level analysis.