Ansys RedHawk

Full-chip Power Integrity and Reliability Analysis

Ansys RedHawk enables you to create robust, low-power, high-performance SoCs, including the ones using the most advanced sub-16 nm FinFETs and 3-D ICs. As the most trusted, industry-standard power noise and reliability closure platform for SoCs, RedHawk has been the only power noise sign-off solution for leading-edge foundries since 2006.


In globally competitive markets for mobile, consumer, automotive and server electronic systems, power efficiency, performance and reliability are the foundation for success. To ensure success, especially for advanced process technology nodes, designers must preserve the integrity of the power delivery network on an integrated circuit against thermal effects, electromigration (EM) and electrostatic discharge (ESD).

Ansys RedHawk, as the de facto standard power integrity and reliability solution, accurately predicts chip power and noise using voltage drop simulation analysis for the entire power delivery network (PDN), from chip to package to board. In addition, with its thermal-aware EM analysis on power/signal lines, chip–package–system cosimulation, SoC ESD integrity verification, and timing (clock, critical path) impact analysis, RedHawk is the most comprehensive reliability solution for integrated circuit design.


High Capacity and Performance

RedHawk delivers the capacity to simulate designs with greater than 100 million instances and more than 2 billion nodes, while maintaining sign-off accuracy that can be obtained only through flat simulation. Its distributed machine processing (DMP) capability takes advantage of the increasing processing power and memory capacity available in a private machine cluster to simulate the entire chip’s RLC network matrices, along with fully distributed and cross-coupled package models. By performing full-chip flat analysis, RedHawk maintains sign-off accuracy for dynamic voltage drop, EM and ESD.

Silicon Validated Sign-off Accuracy

RedHawk software includes an on-die power delivery network (PDN) RLC extraction engine, re-architected for sub-20 nm technologies. It gives you SPICE-accurate transient simulation results at the SoC level using dynamic power models for standard cells and analog/custom IPs. The models simultaneously simulate all power and ground domains, as well as predict the current drawn and voltage seen at every cell in the design.

Sign-off quality SoC dynamic voltage drop analysis requires accurate prediction of current flow inside the package, through the bumps and inside the chip. RedHawk’s CPA feature maps the package to the die layout through pin-to-pin physical connectivity, thereby merging a fully distributed package parasitic network with on-die PDN, enabling package-aware power noise reliability analysis.

RTL-to-GDS Power Noise Closure

RedHawk uses an advanced logic simulation engine for complete RTL-to-GDS sign-off. It contains engines for both static and dynamic simulation, allowing for multiple excitation modes, including mixed-mode, in which different parts of the design can leverage whatever data is available.

RedHawk’s out-of-box VectorLess algorithm enables quick, dynamic hot-spot identification and sign-off coverage without requiring input vectors. The multi-scenario mode in VectorLess simulation enables you to cycle through multiple different activity modes, each meeting the same simulation constraints, without requiring any additional input.

RedHawk works in conjunction with Ansys PowerArtist to offer the industry’s first RTL-to-GDS power noise closure flow. The combined workflow takes in the RTL Power Model (RPM) generated by PowerArtist to perform logic simulation based on register activity recorded in RPM.

Advanced Reliability Sign-off Analysis

For sub-20 nm manufacturing processes, reliability of on-chip interconnects is the most pressing problem. The accuracy and coverage of EM and ESD analyses are extremely important: As currents in wires increase, operating voltages decrease and EM limits shrink.

RedHawk provides full support for power/ground and signal line EM verification, accurately analyzing EM violations while minimizing false positives. When used in conjunction with Ansys PathFinder, RedHawk can perform SoC-level ESD integrity analysis, providing connectivity and interconnect failure checks for all current flow pathways (wires and vias) from an ESD event (HBM, CDM). RedHawk is foundry-certified for power EM, signal EM and SoC ESD sign-off.

Results Analysis and Root Cause Identification

Ansys RedHawk includes a multi-tab, multi-pane GUI that enables faster debug and results analysis by simultaneously displaying various results and tables. It comes with many built-in multi-window settings that you can use to quickly identify causes of design weakness and to isolate a fix to reduce or eliminate a voltage drop or EM hot-spot.

RedHawk Explorer is an integrated, next-generation root-cause identification and debugging tool. It provides data integrity, design weakness and hot-spot analysis information, as well as feedback on how to improve simulation turn-around time.

Low-Power Design Verification

Ansys RedHawk supports simulation and analysis of complex low-power design techniques, such as clock gating, power gating, on-chip regulators and adaptive back-bias network. The software can simultaneously simulate the voltage islands in a chip and consider coupling effects that can be detrimental. The VectorLess engine provides extensive capabilities for modeling operating and transition modes of the clock tree network. As a result, you can predict the effects of transient current on the clock tree and chip performance.

Power Noise Impact on Timing

RedHawk helps you to understand the impact of dynamic voltage drop on timing for clock and critical path. This integrated capability performs fast full-chip-level timing-impact analysis to identify the impacted parts of the circuit, followed by a SPICE-based sign-off simulation for affected path(s) and clock tree(s).

System-Aware Chip and Chip-Aware System Analyses

RedHawk enables you to create a Chip Power Model (CPM), which has revolutionized chip–package–system (CPS) codesign and co-analyses. CPM captures all electrical characteristics of a chip, including switching current and parasitics (resistance, capacitance and inductance), in a compact open SPICE format that can be used by package/PCB-level simulations and optimizations. With CPM, you can perform chip-aware system-level power integrity, EMI and thermal analyses.

RedHawk supports package and PCB models in various industry-standard formats (RLCK, S-parameter, etc.) and varying complexities. Package models created using any industry-standard solution (Ansys SIwave, Sentinel-PSI or Q3D Extractor) can be directly imported to enable system-aware chip analysis.