Ansys PowerArtist

RTL Power Analysis

Ansys PowerArtist is a comprehensive RTL Design-for-Power platform of choice of all leading low-power semiconductor design companies for performing early physical-aware power budgeting and debug, analysis-driven power reduction, power efficiency regressions, and power profiling of live applications with an emulator interface. Delivering an RTL to layout power methodology, PowerArtist also has a seamless interface with Ansys RedHawk enabling a robust power grid and package.

Overview

Power and energy efficiency are paramount in semiconductor design. Compared to gate-level methodologies, RTL provides over 10-times performance, full-chip capacity and reliable accuracy that enables early design decisions for high impact on power. RTL designers working on a variety of applications, from mobile to CPU to networking to automotive ICs, use ANSYS PowerArtist to analyze and reduce power throughout the design development cycle. Our software offers a wide range of capabilities to visualize, estimate, analyze and reduce power. Physical-aware PACE (PowerArtist Calibrator and Estimator) modeling delivers predictable power accuracy at RTL through pre-layout versus final gate-level power numbers, including RTL clock tree synthesis that has achieved within 10 percent to 15 percent clock-power accuracy versus sign-off for 10 nm designs.

PowerArtist automatically identifies block and instance-level sequential and combinational power reduction opportunities across clock network, data path and memory architectures to meet aggressive power targets. Using an interactive power exploration graphical interface, TCL interface on an open-access (OADB)-compatible database, power efficiency metrics, and text reports that detail average and peak power, RTL designers (specifically those new to power) can easily and efficiently debug and track power. Live applications of 100 M+ cycles can be profiled and analyzed for power through a high-performance activity-streaming interface with emulators. Eliminating under- and over-design, PowerArtist RPM (RTL Power Model) interfaces with ANSYS RedHawk, enabling early power grid prototyping and increased sign-off coverage by focusing on power-critical scenarios identified from RTL simulations.

Features

Physical-Aware RTL Power Accuracy

Early power analysis enables high-impact design decisions. PowerArtist's PACE technology and inferencing engine provide consistent accuracy of RTL power versus gate-level sign-off power numbers; all while ensuring rapid turn-around time for multi-million-gate-equivalent RTL power analysis. High-performance engines and simple, streamlined usage flow provide RTL power estimates in minutes, compared to the hours it might take before you the gate-level netlist and the corresponding power numbers are available.

PACE creates a feedback loop between physical and RTL design processes to ensure accuracy and consistency of RTL power estimates. PACE models characterize key power-related design implementation information missing at RTL including clock tree and gating, wire capacitance, and cell distributions. Clocks, in particular, pose a significant challenge; they consume a significant portion of the overall power but exist primarily as an ideal net at RTL. PACE incorporates a complete RTL clock tree synthesis engine for both mesh and tree topologies and has been proven to achieve out-of-the-box RTL clock power within 10-15% of sign-off for 10nm designs.

PACE is especially relevant for sub-20 nm processes, in which traditional RTL approaches are inaccurate and unpredictable and gate-level power analysis is time consuming, difficult to debug and (often) too late in the design cycle.

Comprehensive Power Analysis

PowerArtist provides a complete breakdown of power consumption that enables the designer to identify power hotspots early and throughout the design flow. Standard reports detail power by design hierarchy, clock and power domains, dynamic and leakage, net categories such as register and logic, and by modes of operation.

In addition to supporting industry-standard activity formats (FSDB, VCD, SAIF) for power estimation, the software also provides vectorless means of bringing in user-specified activity for visibility to power even when simulation vectors are not available. Time-based power analysis generates power waveforms and identifies peak power and the time at which the peak power is consumed. Early feedback at RTL can further drive design decisions for optimizing peak power and determining the power grid and decoupling capacitance requirements.

Activity Profiling

Activity has a first order impact on power. It is critical to understand design activity for meaningful power analysis and reduction. Traditional waveform visualization tools focus on individual signals and they fall short of providing a design level view of activity. PowerArtist performs rapid data and clock activity analysis for logical hierarchies and net categories. This allows RTL designers to assess activity coverage across modes of operation and identify the cycles of relevance for subsequent power analysis steps. PowerArtist activity analysis can often lead to power reduction by identifying redundant activity that does not adversely impact the design functionality but leads to wasted power.

Vector profiling can identify vectors that may cause high current or current swings (di/dt) for chip reliability issues. Vector data is captured in PowerArtist's RTL Power Model (RPM), which ANSYS RedHawk uses directly for greater sign-off coverage.

Analysis-driven Automated Power Reduction

PowerArtist's analysis-driven approach to power reduction evaluates power consumption and toggle activity across the RTL design to explore a variety of power-reduction choices at the block and instance levels. PowerArtist looks at topology and activity in the clock tree as well as in the datapath and memory subsystems to identify areas of power reduction.

Whether local or global, the software identifies a wide range of sequential and combinational power-savings opportunities that are complementary to low-power design implementation downstream. For example, dynamic power can be significantly reduced during an idle operation mode by either clock or data gating an entire block(s). Unlike formal approaches that can be limited, PowerArtist sequential power reduction techniques based on stability and observability identify opportunities across an unlimited number of clock cycles and provide the capacity and turnaround time to look across and within hierarchy for multi-million gate-equivalent SoC designs.

All reductions are based on the proven analysis technology that quantifies the amount of power that can be saved upfront before any RTL edit is made. As a result, designers achieve maximum power reduction while minimizing RTL edits and impact on other design parameters such as area and timing. Depending on your preferences, PowerArtist guides the user through a manual RTL rewrite process or automatically generates a power-optimized RTL and synthesis clock gating constraints.

Interactive Power Exploration Framework

PowerArtist enables efficient power debug with powerful visualization and data mining capabilities. For RTL designers new to power, the graphical interface makes it straightforward to quickly spot and debug power hotspots. Interactive power-annotated views allow for cross-probing between the GUI to the exact line of RTL source code. Designers can descend to any level of design hierarchy and query on dynamic versus leakage power, reduction opportunities sorted by technique, area overhead and other metrics. Powerful sort, search and filter, and schematics-based tracing capabilities further assist in identifying the root cause of power consumption and potential fixes.

RTL power provides a power-per-function view unlike the gate level netlist that is implemented using a sea of gates. The RTL view aids the designer to identify where power is consumed and why by tracing functional cones of logic, early in the design flow for a higher impact.

PowerArtist utilizes Si2’s OpenAccess standard database (OADB) and supports an industry-standard TCL API for custom queries. Designers can quickly access power and design properties and generate power- and activity-related reports focusing on the aspects of power that are relevant to their design application.

What-if Power Prototyping

PowerArtist helps designers quickly change RTL design description, power intent, clock-gating directives, etc. to see the impact of these modifications on power consumption. Fast turnaround times of RTL power analysis can enable RTL designers to evaluate the power effectiveness of power gating control signals, without the need for re-running simulations to generate design activity. For the same functionality, different architectures can be evaluated across multiple modes of operation in order to finalize an architecture based on the best power-versus-area tradeoffs.

Power Regression Metrics

Like their functional counterpart, power regressions are intended to guard the design against an undue increase in power. Power regressions have become widely adopted. From the RTL design phase all the way to sign-off, regular regressions locate power-erratic design changes between various versions of RTL when they occur, instead of being lost across thousands of changes. PowerArtist provides multiple power metrics that can be used to track both the power efficiency of a design and its power consumption versus the budget. A commonly used metric is clock gating efficiency (CGE). In addition to static CGE that predicts % gated bits ahead of synthesis, PowerArtist computes cycle-accurate dynamic CGE as a measure of cycles that are not gated yet data is stable.

An important requirement for a regression framework is a power database that allows custom queries to search and compare data across design versions. PowerArtist provides the Tcl interface to its power database in addition to standard utilities that compare multiple runs to highlight design hierarchies where power differs the most.

Power Budgeting for Live Applications

Early visibility into the power profiles of live applications, such as operating system and firmware boot-up, ultra-high definition video frames, etc., is necessary to avoid costly surprises late in the product development cycle. Power inefficiency in any one mode can have a significant impact on the competitiveness of a product or time to market. Emulators run application-level scenarios but writing out activity files of 100M+ cycles on disk slows them down by orders of magnitude.

An emulator-based PAVES (PowerArtist VEctor Streaming) activity streaming flow for power analysis allows RTL designers to compute power profiles of live applications by consuming switching data directly from the emulator, without converting to FSDB/VCD formats - leading up to 5X overall faster turn-around time. More importantly, the flow provides early RTL power visibility and gate-level power sign-off for such long-duration activity scenarios otherwise not possible with conventional file-based activity transfer approaches.

PowerArtist can identify the subset of design nets for which activity is necessary in order to compute accurate power. Activity propagation can deliver the required accuracy for the remaining majority of the design nets. This approach of cutting down design signals that the simulator or emulator has to monitor also delivers significant performance gain both while generating design activity and computing power in file-based activity transfer flows, by cutting down FSDBs by up to 90% of their original size.

RTL-driven Power Grid Integrity

While RTL simulations are designed to handle millions of cycles of simulation, ensuring power grid integrity requires a transient analysis that can focus on a few nanoseconds of activity. Ansys PowerArtist leverages fast, high-capacity RTL simulation engines to rapidly identify the clock periods and activity modes that are likely to cause increased voltage drop or reliability issues.

The relevant information is captured into an RTL Power Model (RPM), which Ansys RedHawk uses to enable multiple downstream simulations, ranging from early power grid prototyping for optimal sizing to cycle-accurate static and dynamic voltage drop analyses for increased sign-off confidence. An early PACE-based RPM also enables RedHawk to generate an early Chip Power Model (CPM) for chip-package co-design, well before the design layout is ready.