Ansys PathFinder

Overview

Industry surveys indicate that up to 35 percent of integrated circuit (IC) field failures are ESD related. The convergence of advanced process technology, increasing levels of digital and analog integration, higher operating frequencies, proliferation of handheld devices, and advanced package designs with tighter pitch and fewer layers exacerbate the impact of ESD-induced failures in integrated circuits.

Using full-chip-level modeling techniques, Ansys PathFinder can determine if a design meets ESD guidelines; it can identify weak areas of the design (layout or circuit) that are most vulnerable. The software performs early prototyping and design exploration, especially when clamp cells are inserted inside the core region of the chip. PathFinder can model an ESD event and analyze the design to predict which clamp cells will be effective and which cells will not.

Features

Integrated Single-Pass Simulation and Result Analysis

PathFinder enables a streamlined, single-pass-use model — reading in design data, setting up ESD rules, performing extraction and ESD simulations, analyzing root cause, and providing fix and optimization feedbacks — within a single-tool environment. The software uses industry-standard data formats, such as GDS and DEF. It allows considerable flexibility in specifying various rules and associated parameters that are checked, enabling designers to conduct a wide range of validation.

Full-Chip Capacity

PathFinder can perform ESD integrity checks on very large SOC designs with more than 100 M+ instances. It handles hundreds of power/ground/signal nets and performs resistance and current density simulations in a single simulation. Full-chip ESD simulations take from a few hours to a day’s turn-around time, depending on size, number of metal layers, complexity of PG network, number of power/ground/signal nets and number of ESD devices. PathFinder incorporates multithreading and distributed computing options to handle ultra-large designs.

Layout-Based Analysis & Root-Cause Identification

As a layout-based ESD analysis and sign-off solution, ANSYS PathFinder identifies layout issues and connectivity imbalances that might result in an ESD-event-induced failure. Examples include bumps not connected to any ESD clamps or clamps not hooked up to the power/ground network. By traversing every conduction pathway between any two relevant points inside the chip, PathFinder verifies connection robustness, checking electrical characteristics against foundry- or user-specified limits. For example, it calculates resistance for all possible electrical paths between bump and clamp to verify that a given connection does not exceed a specified resistance limit. Using the chip design database, foundry-specified technology parameters, and ESD sign-off limits, our software quickly and accurately computes the required electrical parameters and verifies against specified limits. PathFinder provides extensive GUI-based debugging capabilities that help designers to identify layout issues quickly and perform what-if analyses before committing to a fix. Users can generate pass─fail reports that can be cross-probed to the layout in the GUI.

Comprehensive Coverage

PathFinder’s ESD analysis, verification and sign-off coverage is applicable from the initial design phase to tape-out. During the floor planning stage, designers can perform trade-off analysis by optimizing core clamp placement and exploring what-if analysis. This enables the team to efficiently plan resources, a critical task as designs require more clamps and/or clamp sizes don’t scale as effectively. Clamps embedded in I/O ring or custom IP are often not verified. Instead, design teams follow engineering guidelines and rely on correct-by-construction principles. PathFinder performs layout-based sign-off checks by reading in IP or I/O-level layout data, enabling optimization of I/O pad and clamp placements. For an IP, you can use PathFinder to perform transient ESD simulations for better understanding of ESD discharge paths and identification of stressed device junctions. To identify weaknesses introduced during I/O and/or IP integration, an ESD macro-model that embeds ESD device models can be generated and seamlessly consumed for full chip-level ESD sign-off checks.

HBM/MM ESD Events

Ansys PathFinder mimics human body model (HBM)/machine model (MM) ESD events during ESD discharge by propagating the zap current through the power/ground network, identifying bottlenecks in the layout. By modeling the injection of current into any pad and subsequent flow of current through on-chip interconnects, the software identifies pin-clamp-pin paths that are ineffective in handling the high current present during an ESD event. It estimates current density in wires connected to those pads and checks against foundry-specified limits, highlighting issues such as imbalanced connections on clamp/diode fingers and insufficient vias or metal segments that are too narrow in the ESD discharge path. Unlike with DRC-based checks, PathFinder’s interconnect failure analysis provides a comprehensive way to cover every possible wire segment/via in the ESD discharge path.

SPICE-Correlated Accuracy

PathFinder delivers accurate transient simulation with the ability to model the die substrate and snap-back behavior of complex ESD devices. At the IP level, the software extracts the power/ground and substrate RC network and performs transient simulations. It takes in SPICE models for functional and parasitic devices (such as well-diodes) and accurately performs transient simulation at picosecond resolution with SPICE-correlated results. Clamps with snap-back behavior often have convergence issues in SPICE; PathFinder’s simulation engine is customized to handle snap-back behavior of the clamp devices to accurately model ESD device triggering and identify the stressed device junctions during ESD events.